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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-12-07 18:20:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 17:53:21 +0000 |
| commit | 105495f37e0a5e063b4ca414e84f344b13cc28d4 (patch) | |
| tree | 866fc0497e6817b5f535bc6b0e87646d6a3b0691 /src/soc | |
| parent | c7ab9f410cfea6bd6260ecb8ac336f87f4cf3736 (diff) | |
| download | coreboot-105495f37e0a5e063b4ca414e84f344b13cc28d4.tar.gz coreboot-105495f37e0a5e063b4ca414e84f344b13cc28d4.tar.bz2 coreboot-105495f37e0a5e063b4ca414e84f344b13cc28d4.zip | |
soc/amd/stoneyridge/southbridge: drop ENV_X86 check
Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will
run on the x86 cores. On Picasso and later, the Chromebooks run verstage
on the PSP which is an ARM V7 core which needs some special handling
cases in the code, but this doesn't apply to Stoneyridge.
TEST=Timeless build results in an identical image for Google/Careena.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 63bfd832b39e..3b2cba6352c0 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -230,8 +230,7 @@ void fch_clk_output_48Mhz(u32 osc) static void sb_init_spi_base(void) { /* Make sure the base address is predictable */ - if (ENV_X86) - lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_set_spibase(SPI_BASE_ADDRESS); lpc_enable_spi_rom(SPI_ROM_ENABLE); } |