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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-17 10:22:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2022-07-18 12:44:32 +0000 |
| commit | 10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc (patch) | |
| tree | 955d62a8b6e02c309b5b960fbbcf5644eb1f46e8 /src/soc | |
| parent | bb5ccbd42fd3e702f71017dd186ae98278ffeeac (diff) | |
| download | coreboot-10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc.tar.gz coreboot-10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc.tar.bz2 coreboot-10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc.zip | |
treewide: Don't add bits
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/aoac.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/QuarkNcSocId.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index f4a00c73a733..455f32d9e685 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -10,7 +10,7 @@ #define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) /* Bit definitions for Device D3 Control AOACx0000[40...7E; even byte addresses] */ -#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) +#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) | BIT(1)) #define FCH_AOAC_D0_UNINITIALIZED 0 #define FCH_AOAC_D0_INITIALIZED 1 #define FCH_AOAC_D1_2_3_WARM 2 diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index e4015a2e7c72..4a62c04eeb8a 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -807,7 +807,7 @@ #define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 #define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) #define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) -#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) +#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 | BIT1) // Opcode Menu Configuration //R_OPMENU #define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) |