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| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2020-02-06 14:20:57 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-18 16:51:57 +0000 |
| commit | 11637452cc093a64e078edebe1d6e18b462c3757 (patch) | |
| tree | f982350f69813939d97b8caf8f8fe326b51fdcac /src/soc | |
| parent | 31b081a48d1cd654624c17b32265bd1e079e3912 (diff) | |
| download | coreboot-11637452cc093a64e078edebe1d6e18b462c3757.tar.gz coreboot-11637452cc093a64e078edebe1d6e18b462c3757.tar.bz2 coreboot-11637452cc093a64e078edebe1d6e18b462c3757.zip | |
soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.
BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci
Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 23 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index f3f700f1462f..a8be407d234e 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -186,6 +186,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode; + /* USB4/TBT */ + for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { + dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); + if (dev) + params->ITbtPcieRootPortEn[i] = dev->enabled; + else + params->ITbtPcieRootPortEn[i] = 0; + } + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index e275e59fcc9c..95f637e4ec3b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -120,6 +120,29 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + if (dev) + m_cfg->TcssItbtPcie0En = dev->enabled; + else + m_cfg->TcssItbtPcie0En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + if (dev) + m_cfg->TcssItbtPcie1En = dev->enabled; + else + m_cfg->TcssItbtPcie1En = 0; + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + if (dev) + m_cfg->TcssItbtPcie2En = dev->enabled; + else + m_cfg->TcssItbtPcie2En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + if (dev) + m_cfg->TcssItbtPcie3En = dev->enabled; + else + m_cfg->TcssItbtPcie3En = 0; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ |