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author | Angel Pons <th3fanbus@gmail.com> | 2021-08-30 10:00:31 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-03 00:11:02 +0000 |
commit | 1b3462749b064ea46859273ea4670bf6abe414c3 (patch) | |
tree | 7142bd182c2c0af80210b854cfccf21cf930faa3 /src/soc | |
parent | 28a16d960c31e853ded415ff9159e0dc409d2a90 (diff) | |
download | coreboot-1b3462749b064ea46859273ea4670bf6abe414c3.tar.gz coreboot-1b3462749b064ea46859273ea4670bf6abe414c3.tar.bz2 coreboot-1b3462749b064ea46859273ea4670bf6abe414c3.zip |
src/*: Specify type of `DIMM_MAX` once
Specify the type of the `DIMM_MAX` Kconfig symbol once.
Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 3e3b8c13227d..51fc927fc0f4 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -105,7 +105,6 @@ config CPU_BCLK_MHZ # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel # Default value is set to one socket, full config. config DIMM_MAX - int default 12 # DDR4 |