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| author | Julius Werner <jwerner@chromium.org> | 2021-12-29 08:32:28 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2022-01-08 00:41:02 +0000 |
| commit | 20ba6e4834b8bf1fe9fa7d6a45f27e8d89ef6bc4 (patch) | |
| tree | 5a41167cb68e6f084f25d2a631cd4b6d2b63675a /src/soc | |
| parent | 2360d7c2771536b785dbcb435f135c5eff713a46 (diff) | |
| download | coreboot-20ba6e4834b8bf1fe9fa7d6a45f27e8d89ef6bc4.tar.gz coreboot-20ba6e4834b8bf1fe9fa7d6a45f27e8d89ef6bc4.tar.bz2 coreboot-20ba6e4834b8bf1fe9fa7d6a45f27e8d89ef6bc4.zip | |
sc7180: Increase bootblock size and add pre-RAM TCPA buffer
In order to make SC7180 boards compatbile with some optional Kconfigs,
increase the bootblock size a bit and add room for a TCPA log buffer to
memlayout. The large pre-RAM CBFS cache wasn't really needed anymore
anyway since we switched QcLib to use LZ4 compression.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/sc7180/memlayout.ld | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 1b9044f691a5..938f3e1e4222 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -31,8 +31,9 @@ SECTIONS BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 83K, 4K) WATCHDOG_TOMBSTONE(0x14814FFC, 4) - BOOTBLOCK(0x14815000, 40K) - PRERAM_CBFS_CACHE(0x1481F000, 70K) + BOOTBLOCK(0x14815000, 48K) + TPM_TCPA_LOG(0x14821000, 2K) + PRERAM_CBFS_CACHE(0x14821800, 60K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) TIMESTAMP(0x14838800, 1K) TTB(0x14839000, 56K) |