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| author | Chen-Tsung Hsieh <chentsung@chromium.org> | 2021-09-06 12:58:39 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-08 10:16:53 +0000 |
| commit | 229e6bc95f177c78aa9a96e94708ba5d186186eb (patch) | |
| tree | c455282cd7bfed555eb09d17c01c6f4597e97de1 /src/soc | |
| parent | f88b90f6a9031ddf28c041628534efbfce01a39f (diff) | |
| download | coreboot-229e6bc95f177c78aa9a96e94708ba5d186186eb.tar.gz coreboot-229e6bc95f177c78aa9a96e94708ba5d186186eb.tar.bz2 coreboot-229e6bc95f177c78aa9a96e94708ba5d186186eb.zip | |
mb/google/cherry: Fix incorrect timestamps in eventlog
The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.
BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8195/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 3439001cbadf..d15d4760c2f1 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -67,6 +67,8 @@ ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c ramstage-y += ../common/pll.c pll.c +ramstage-y += ../common/pmif.c +ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/sspm.c |