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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-05 13:46:40 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-13 17:39:30 +0000 |
| commit | 2526be8db381addd398afae55370127f3a747cdc (patch) | |
| tree | 445c0ea8847b5b8a7137e5528ce1c727319924bf /src/soc | |
| parent | 5705b63a08d28ddf8c5a22600e19aa8dd8513614 (diff) | |
| download | coreboot-2526be8db381addd398afae55370127f3a747cdc.tar.gz coreboot-2526be8db381addd398afae55370127f3a747cdc.tar.bz2 coreboot-2526be8db381addd398afae55370127f3a747cdc.zip | |
soc/amd/common/block/spi: Support fast speed override
Add support to override SPI ROM fast speed based on board version. This
will allow boards to start at lower speeds during bringup and then
switch to higher speeds after assessing the signal integrity. Also
implement a default no-op override.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi.c | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eaea0f79c927..35a3782f7a26 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -117,4 +117,5 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); void fch_spi_config_modes(void); +void mainboard_spi_fast_speed_override(uint8_t *fast_speed); #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 51787fae9266..fad8cd9951dd 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -50,6 +50,11 @@ void show_spi_speeds_and_modes(void) printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); } +void __weak mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + /* No overriding SPI speeds. */ +} + static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) { uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M, @@ -102,6 +107,7 @@ void fch_spi_config_modes(void) read_mode = CONFIG_EFS_SPI_READ_MODE; fast_speed = CONFIG_EFS_SPI_SPEED; } + mainboard_spi_fast_speed_override(&fast_speed); if (fast_speed != CONFIG_EFS_SPI_SPEED) { normal_speed = lower_speed(normal_speed, fast_speed); |