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| author | Bora Guvendik <bora.guvendik@intel.com> | 2019-06-24 14:33:31 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-13 09:56:54 +0000 |
| commit | 349b6a1152a7cae1be530a9a037aa8d5138160d5 (patch) | |
| tree | 32e76820411a9f61a9d65a481eb21fdb82aa4709 /src/soc | |
| parent | 48427512d6f8248f95aab5cff95f1c67f984258d (diff) | |
| download | coreboot-349b6a1152a7cae1be530a9a037aa8d5138160d5.tar.gz coreboot-349b6a1152a7cae1be530a9a037aa8d5138160d5.tar.bz2 coreboot-349b6a1152a7cae1be530a9a037aa8d5138160d5.zip | |
soc/intel/cannonlake: Allow coreboot to reserve stack for fsp
FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.
TEST=Boot to OS on WHL platform
Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fc3f2ac3c2a3..c1fda951c22b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -29,6 +29,7 @@ config SOC_INTEL_COFFEELAKE config SOC_INTEL_WHISKEYLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK help Intel Whiskeylake support |