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| author | Robert Zieba <robertzieba@google.com> | 2022-09-15 15:25:55 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-09 19:38:14 +0000 |
| commit | 3b28aefa1d45d7a2531fb715c58dc40f75b53745 (patch) | |
| tree | a0c38b76b5f9b2de45f79a10c11bc72de5e868b2 /src/soc | |
| parent | 88fb0a1cb585e8f887a2d40c6919b6840d47fa25 (diff) | |
| download | coreboot-3b28aefa1d45d7a2531fb715c58dc40f75b53745.tar.gz coreboot-3b28aefa1d45d7a2531fb715c58dc40f75b53745.tar.bz2 coreboot-3b28aefa1d45d7a2531fb715c58dc40f75b53745.zip | |
soc/amd/mendocino: Set up SoC-specific XHCI defines
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.
BUG=b:186792595
TEST=builds
Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67938
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/mendocino/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/xhci.h | 15 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 356623f0cf2b..737a8dbfa8d9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -74,6 +74,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_BLOCK_XHCI select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI diff --git a/src/soc/amd/mendocino/include/soc/xhci.h b/src/soc/amd/mendocino/include/soc/xhci.h new file mode 100644 index 000000000000..b554c98219aa --- /dev/null +++ b/src/soc/amd/mendocino/include/soc/xhci.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_MENDOCINO_XHCI_H +#define AMD_MENDOCINO_XHCI_H + +#define SOC_XHCI_0 DEV_PTR(xhci_0) +#define SOC_XHCI_1 DEV_PTR(xhci_1) +#define SOC_XHCI_2 DEV_PTR(xhci_2) +#define SOC_XHCI_3 NULL +#define SOC_XHCI_4 NULL +#define SOC_XHCI_5 NULL +#define SOC_XHCI_6 NULL +#define SOC_XHCI_7 NULL + +#endif /* AMD_MENDOCINO_XHCI_H */ |