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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 16:08:57 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-08 13:00:29 +0000 |
| commit | 4892d737e3050a645083b946b5f7e884479c1a8f (patch) | |
| tree | 206f4818c334e721e939e39c1b0326356099f404 /src/soc | |
| parent | 84fb9eac96dc15016820eec6fc6de91f4a243205 (diff) | |
| download | coreboot-4892d737e3050a645083b946b5f7e884479c1a8f.tar.gz coreboot-4892d737e3050a645083b946b5f7e884479c1a8f.tar.bz2 coreboot-4892d737e3050a645083b946b5f7e884479c1a8f.zip | |
soc/amd/stoneyridge/romstage: pass C state control IO base address
Instead of hoping that the default the C state control IO address in
binaryPI won't interfere with any other IO space usage in coreboot,
assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform
config structure element to make sure that binaryPI will use a known
address for the IO port based C state control. binaryPI will write this
address to the MSR_CSTATE_ADDRESS and will then also use these IO ports
in the _CST packages in the PSTATE SSDT, so changing this won't cause
a mismatch between those two.
The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on
Careena is 0x1770, so this didn't collide with any other IO space
registers, but it's still much better to tell binaryPI which exact IO
addresses to use.
TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL
IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in
the _CST package entry for the second C state which are both the
expected values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 31cd12bb3e4e..0977bb360de3 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -30,6 +30,7 @@ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index efa256fb1489..460218e73c56 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -22,6 +22,7 @@ #include <program_loading.h> #include <romstage_common.h> #include <romstage_handoff.h> +#include <soc/iomap.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> @@ -190,6 +191,10 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) platform->PkgPwrLimitAC = cfg->stapm_power_mw; platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; } + + /* Make binaryPi use ACPI_CSTATE_CONTROL as C state control IO range. It gets written + into MSR_CSTATE_ADDRESS and used in the _CST packages in the PSTATE SSDT. */ + platform->CStateIoBaseAddress = ACPI_CSTATE_CONTROL; } static void migrate_power_state(int is_recovery) |