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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-12-04 02:24:31 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-14 18:42:19 +0000 |
| commit | 551bd92b2b33fb71e74eb8d22db3aea69280a9b7 (patch) | |
| tree | da207596e6962fd3f8bd6c821da5dff923c30780 /src/soc | |
| parent | 1a2b70284895a9daef667aada307405039dc8cce (diff) | |
| download | coreboot-551bd92b2b33fb71e74eb8d22db3aea69280a9b7.tar.gz coreboot-551bd92b2b33fb71e74eb8d22db3aea69280a9b7.tar.bz2 coreboot-551bd92b2b33fb71e74eb8d22db3aea69280a9b7.zip | |
soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/jasperlake/romstage/romstage.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 1fa6c2d18041..6d34b438cf9c 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -135,6 +135,16 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } } |