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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 23:37:58 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:52 +0000 |
| commit | 62afdb675a49bfebbdd4f186f696c15a56d64348 (patch) | |
| tree | 50fa03f35315cb3e6e13c3960bd1b6d5c0aae288 /src/soc | |
| parent | 45b6080561748fe579c8ee901811cf4043383c2f (diff) | |
| download | coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.tar.gz coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.tar.bz2 coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.zip | |
soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/espi_util.c | 33 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/espi.h | 4 |
3 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 050ba44be98c..5fda4b0b826d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -10,6 +10,7 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c diff --git a/src/soc/amd/cezanne/espi_util.c b/src/soc/amd/cezanne/espi_util.c new file mode 100644 index 000000000000..ceb87243e2d0 --- /dev/null +++ b/src/soc/amd/cezanne/espi_util.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/lpc.h> +#include <device/pci_ops.h> +#include <soc/espi.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> +#include <types.h> + +void espi_disable_lpc_ldrq(void) +{ + /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped + on Picasso and older compared to Renoir/Cezanne and newer */ + uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); +} + +void espi_switch_to_spi2_pads(void) +{ + /* Use SPI2 pins for eSPI */ + uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); + + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); +} diff --git a/src/soc/amd/cezanne/include/soc/espi.h b/src/soc/amd/cezanne/include/soc/espi.h new file mode 100644 index 000000000000..9836ef7686d1 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/espi.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void espi_disable_lpc_ldrq(void); +void espi_switch_to_spi2_pads(void); |