diff options
author | Philipp Deppenwiese <zaolin@das-labor.org> | 2017-10-18 17:13:07 +0200 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-18 01:35:31 +0000 |
commit | 64e2d19082636de9e82674ccfca574269bb34712 (patch) | |
tree | dfe44c9b1cebbb611b99474c1ee096e23f930796 /src/soc | |
parent | 4fef7818ecd002e5971ea6287e402fd9276b7266 (diff) | |
download | coreboot-64e2d19082636de9e82674ccfca574269bb34712.tar.gz coreboot-64e2d19082636de9e82674ccfca574269bb34712.tar.bz2 coreboot-64e2d19082636de9e82674ccfca574269bb34712.zip |
security/tpm: Move tpm TSS and TSPI layer to security section
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 2 | ||||
-rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 2 | ||||
-rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 2 | ||||
-rw-r--r-- | src/soc/intel/common/tpm_tis.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9990d8425778..d8e6449dc6ce 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -30,7 +30,7 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 0f82c49999fa..12a15304a255 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -43,7 +43,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> -#include <tpm.h> +#include <security/tpm/tpm.h> void program_base_addresses(void) { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 1417b802cf24..fa4c1eac6238 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -25,7 +25,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <tpm.h> +#include <security/tpm/tpm.h> #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> diff --git a/src/soc/intel/common/tpm_tis.c b/src/soc/intel/common/tpm_tis.c index ed57cef4882d..f088c0d16abc 100644 --- a/src/soc/intel/common/tpm_tis.c +++ b/src/soc/intel/common/tpm_tis.c @@ -14,7 +14,7 @@ */ #include <arch/acpi.h> -#include <tpm.h> +#include <security/tpm/tpm.h> int tis_plat_irq_status(void) { |