diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-11 10:14:26 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-21 16:08:13 +0000 |
| commit | 6a4f5739c8cf2ede8e9b6298a610b60621152eca (patch) | |
| tree | 2cba5019329f691110b311072ba28a44ec3a0713 /src/soc | |
| parent | 38fcf40330adbbb3b93c29eb809a9a56504a63a5 (diff) | |
| download | coreboot-6a4f5739c8cf2ede8e9b6298a610b60621152eca.tar.gz coreboot-6a4f5739c8cf2ede8e9b6298a610b60621152eca.tar.bz2 coreboot-6a4f5739c8cf2ede8e9b6298a610b60621152eca.zip | |
soc/intel/common/gpio: Use const variable to get gpio bitmask
This patch introduces a `const bit_mask` variable to hold the gpio
PAD mask value prior to sending the lock configuration command using
the sideband interface.
Additionally, this patch fixes the PAD lock overridden issue as below:
Without this code change every consecutive PAD lock operation resets
other bits in that register as below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0x8
After Locking pad 4 , pcr_read=0x10
After Locking pad 5 , pcr_read=0x20
After Locking pad 6 , pcr_read=0x40
After Locking pad 7 , pcr_read=0x80
After Locking pad 8 , pcr_read=0x100
With this code change all previous lock bits are getting preserved as
below:
After Locking pad 2 , pcr_read=0x4
After Locking pad 3 , pcr_read=0xc
After Locking pad 4 , pcr_read=0x1c
After Locking pad 5 , pcr_read=0x3c
After Locking pad 6 , pcr_read=0x7c
After Locking pad 7 , pcr_read=0xfc
After Locking pad 8 , pcr_read=0x1fc
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I342a666aa2d34bcc8ba33460396d1248f0c0f89f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60999
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index e70fcaab482f..1d28905a5ebf 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -526,7 +526,7 @@ int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count) /* PADCFGLOCK and PADCFGLOCKTX registers for each community are contiguous */ offset += gpio_group_index_scaled(comm, rel_pad, 2 * sizeof(uint32_t)); - data = gpio_bitmask_within_group(comm, rel_pad); + const uint32_t bit_mask = gpio_bitmask_within_group(comm, rel_pad); msg.pid = comm->port; msg.offset = offset; @@ -534,6 +534,7 @@ int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count) if (CONFIG(DEBUG_GPIO)) printk(BIOS_INFO, "%s: Locking pad %d configuration\n", __func__, pad); + data = pcr_read32(msg.pid, msg.offset) | bit_mask; status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data, &response); if ((err = sideband_msg_err(status, response)) != 0) { err_response = err; @@ -546,6 +547,7 @@ int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count) printk(BIOS_INFO, "%s: Locking pad %d TX state\n", __func__, pad); msg.offset += sizeof(uint32_t); + data = pcr_read32(msg.pid, msg.offset) | bit_mask; status = pcr_execute_sideband_msg(PCH_DEV_P2SB, &msg, &data, &response); if ((err = sideband_msg_err(status, response)) != 0) { err_response = err; |