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| author | Angel Pons <th3fanbus@gmail.com> | 2021-10-11 14:01:55 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-10-15 16:46:57 +0000 |
| commit | a0f8dc3bd55d4706606e14173bb9afaa97049287 (patch) | |
| tree | a2de0f29d4fb1412c984a8ff89d2ec761f1f289c /src/soc | |
| parent | 9573c0ed3adbca869cf1b88312a10cc72b756547 (diff) | |
| download | coreboot-a0f8dc3bd55d4706606e14173bb9afaa97049287.tar.gz coreboot-a0f8dc3bd55d4706606e14173bb9afaa97049287.tar.bz2 coreboot-a0f8dc3bd55d4706606e14173bb9afaa97049287.zip | |
soc/intel/cannonlake: Enable Energy/Performance Bias control
Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control.
TEST=Boot and verify EPB is enabled in coreboot log:
cpu: energy policy set to 6
Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 99fcadd58185..8c8cad098e51 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -51,6 +51,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } |