soc/intel/braswell: Use {read,write}32p()

Change-Id: I00894565efc405a47348236ad7df50071a843487
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77972
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 23 insertions, 23 deletions

diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c
index 677007d52be9..0a2e001898f6 100644
--- a/src/soc/intel/braswell/gpio_support.c
+++ b/src/soc/intel/braswell/gpio_support.c
@@ -146,5 +146,5 @@ int gpio_get(gpio_t gpio_num)
 
 int get_gpio(int community_base, int pad0_offset)
 {
-	return (read32((void *)(community_base + pad0_offset))) & PAD_RX_BIT;
+	return (read32p(community_base + pad0_offset)) & PAD_RX_BIT;
 }
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index ea7f0caf2eb0..f00eb4b869b2 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -319,12 +319,12 @@ void clear_pmc_status(void)
 	uint32_t prsts;
 	uint32_t gen_pmcon1;
 
-	prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
-	gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+	prsts = read32p(PMC_BASE_ADDRESS + PRSTS);
+	gen_pmcon1 = read32p(PMC_BASE_ADDRESS + GEN_PMCON1);
 
 	/* Clear the status bits. The RPS field is cleared on a 0 write. */
-	write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
-	write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts);
+	write32p(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
+	write32p(PMC_BASE_ADDRESS + PRSTS, prsts);
 }
 
 int rtc_failure(void)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index a1623e13f968..233df3fc57a8 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -37,9 +37,9 @@ struct chipset_power_state *fill_power_state(void)
 	power_state.gpe0_en  = inl(ACPI_BASE_ADDRESS + GPE0_EN);
 	power_state.tco_sts  = inl(ACPI_BASE_ADDRESS + TCO_STS);
 
-	power_state.prsts      = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
-	power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
-	power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2));
+	power_state.prsts      = read32p(PMC_BASE_ADDRESS + PRSTS);
+	power_state.gen_pmcon1 = read32p(PMC_BASE_ADDRESS + GEN_PMCON1);
+	power_state.gen_pmcon2 = read32p(PMC_BASE_ADDRESS + GEN_PMCON2);
 
 	power_state.prev_sleep_state = chipset_prev_sleep_state(&power_state);
 
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index f2151a9bb316..d2588cf766f8 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -60,24 +60,24 @@ static void busmaster_disable_on_bus(int bus)
 static void tristate_gpios(uint32_t val)
 {
 	/* Tri-state eMMC */
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val);
 
 	/* Tri-state HDMI */
-	write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
 
 	/* Tri-state CFIO 139 and 140 */
-	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val);
+	write32p(COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
 }
 
 static void southbridge_smi_sleep(void)
@@ -136,7 +136,7 @@ static void southbridge_smi_sleep(void)
 	}
 
 	/* Clear pending wake status bit to avoid immediate wake */
-	write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200)));
+	write32p(0xfed88000 + 0x0200, read32p(0xfed88000 + 0x0200));
 
 	/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
 	if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))