diff options
| author | Tim Van Patten <timvp@google.com> | 2022-09-06 09:56:52 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-19 09:54:00 +0000 |
| commit | b06873f77cba236c766a38fe58115a956c600397 (patch) | |
| tree | f96ca0203bbd2ff80daa26f581fd7b59d95564f2 /src/soc | |
| parent | a90aebbf2a471b901bd1aa40e12e4f6a021b8ecc (diff) | |
| download | coreboot-b06873f77cba236c766a38fe58115a956c600397.tar.gz coreboot-b06873f77cba236c766a38fe58115a956c600397.tar.bz2 coreboot-b06873f77cba236c766a38fe58115a956c600397.zip | |
soc/amd/mendocino: Add VRM limit DPTC registers
Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.
b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/mendocino/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 68629d77a985..15012fd4da5c 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -56,6 +56,7 @@ struct soc_amd_mendocino_config { uint16_t stt_error_coeff; uint16_t stt_error_rate_coefficient; + /* Default */ uint8_t stapm_boost; uint32_t stapm_time_constant_s; uint32_t apu_only_sppt_limit; @@ -64,6 +65,9 @@ struct soc_amd_mendocino_config { uint32_t slow_ppt_limit_mW; uint32_t slow_ppt_time_constant_s; uint32_t thermctl_limit_degreeC; + uint32_t vrm_current_limit_mA; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; uint8_t smartshift_enable; |