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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-04 19:54:32 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-07 05:47:33 +0000 |
commit | b2a5f0b9c2eb79f1a9d4fe4f87f1460c1be7fa6d (patch) | |
tree | 37b8bd523e8a672853bba15804cb161278824693 /src/soc | |
parent | fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 (diff) | |
download | coreboot-b2a5f0b9c2eb79f1a9d4fe4f87f1460c1be7fa6d.tar.gz coreboot-b2a5f0b9c2eb79f1a9d4fe4f87f1460c1be7fa6d.tar.bz2 coreboot-b2a5f0b9c2eb79f1a9d4fe4f87f1460c1be7fa6d.zip |
cpu/x86/smm: Promote smm_subregion()
No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.
Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
25 files changed, 19 insertions, 77 deletions
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index bee2b4b49fcb..84f4729b20eb 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 65705b93f331..57373c9a0882 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -99,29 +99,8 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - void amd_initcpuio(void); -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 7c855bb1e181..8eb2e39883f8 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 950b41f5a3d5..458886d70c51 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index f751dc80466a..9961153b0bd6 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <device/device.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 60a6ea22bbeb..a0d7ce88dd1e 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -99,27 +99,6 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 7c855bb1e181..8eb2e39883f8 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 000d100fa358..4f38dbf13810 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,6 +19,7 @@ #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 625d956ea776..f3aa40c1a3c2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,10 +29,10 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 66f4dda02d6e..a4101b7446a5 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,8 +18,8 @@ #include <assert.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/smm.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7b10222b4b40..97e2f83bdd50 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -27,10 +27,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/pae.h> #include <delay.h> +#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> -#include <fsp/memmap.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11db171..bde4b1c418c2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -26,7 +26,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <reg_script.h> #include <soc/iosf.h> #include <soc/msr.h> diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index a4692ceb652a..69bbe5872760 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -15,7 +15,7 @@ */ #include <cbmem.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> #include <soc/smm.h> diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 92674486973c..e37e0d6e7d4c 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -21,8 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <fsp/memmap.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f0b779..bf58b9c12cea 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46800a2..25ff8f4ec90a 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -32,7 +32,5 @@ */ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); -/* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index a2a7c164c883..8ccd13a46e86 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,7 +18,6 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fc1024afa7fe..d6ddcc054846 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -21,6 +21,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/turbo.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index ca01cf8def86..a020891dd579 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -24,25 +24,6 @@ struct smm_relocation_attrs { uint32_t smrr_mask; }; -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 256192261d90..d94d1f3ddd49 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -16,12 +16,12 @@ #include <cbmem.h> #include <assert.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <soc/smm.h> #include <lib.h> /* Returns base of requested region encoded in the system agent. */ diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2ad78a02df39..6950620a8744 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -20,6 +20,7 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> @@ -29,7 +30,6 @@ #include <soc/pmc.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/smm.h> #include <soc/soc_util.h> #include <soc/hob_mem.h> diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593f7277..75cb4eae3c9d 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -18,7 +18,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e9766c07f..1000ce830c99 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -19,7 +19,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> -#include <fsp/memmap.h> +#include <cpu/x86/smm.h> #include <intelblocks/smihandler.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 7a39b6748aa6..f69a88b30fce 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -18,9 +18,9 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/memmap.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/msr.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index bb86c6300d6b..b3781e2a6590 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,11 +18,11 @@ #include <assert.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> -#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <memory_info.h> #include <smbios.h> |