diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-03-01 14:44:32 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 00:53:06 +0000 |
| commit | b77ea4c54aaffc8ab1016f79696c6defe0db472f (patch) | |
| tree | 75638d132fd19888c9c433e5fd5c15af5c514319 /src/soc | |
| parent | b94cc7d3672fd1756ae252c6505da716343a3c41 (diff) | |
| download | coreboot-b77ea4c54aaffc8ab1016f79696c6defe0db472f.tar.gz coreboot-b77ea4c54aaffc8ab1016f79696c6defe0db472f.tar.bz2 coreboot-b77ea4c54aaffc8ab1016f79696c6defe0db472f.zip | |
soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headers
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/soc_msr.h | 32 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/msr.h | 19 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h | 35 |
3 files changed, 70 insertions, 16 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_msr.h new file mode 100644 index 000000000000..f435e4e806ba --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_msr.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_MSR_CPX_H_ +#define _SOC_MSR_CPX_H_ + +/* MCA_ERROR_CONTROL */ +#define U2C_SMI_ENABLED (1 << 2) + +/* CPX has banks 0-22 */ +#define IA32_MC20_CTL2 0x294 +#define IA32_MC21_CTL2 0x295 +#define IA32_MC22_CTL2 0x29 + +/* MSR_POWER_CTL (SKX and CPX) */ +#define FAST_BRK_SNP_ENABLE_SHIFT 3 +#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) +#define FAST_BRK_INT_ENABLE_SHIFT 4 +#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 +#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) +#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 +#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) +#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 +#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) +#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 +#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) +#define LTR_IIO_DISABLE_SHIFT 29 +#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) + +#endif /* _SOC_MSR_CPX_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index 9a8b641b4937..377d33b402ea 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -35,22 +35,6 @@ #define MSR_POWER_CTL 0x1fc #define BIDIR_PROCHOT_ENABLE_SHIFT 0 #define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) -#define FAST_BRK_SNP_ENABLE_SHIFT 3 -#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) -#define FAST_BRK_INT_ENABLE_SHIFT 4 -#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) -#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 -#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) -#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 -#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) -#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 -#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) -#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 -#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) -#define PROCHOT_LOCK_SHIFT 27 -#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) -#define LTR_IIO_DISABLE_SHIFT 29 -#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) /* MSR_IA32_PERF_CTRL (0x199) bits */ #define MSR_IA32_PERF_CTRL 0x199 @@ -99,4 +83,7 @@ #define MSR_PPIN_CAP_SHIFT 23 #define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) +/* SOC-specific #defines may use the above definitions */ +#include <soc/soc_msr.h> + #endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h new file mode 100644 index 000000000000..e524cead92b2 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_MSR_SKX_H_ +#define _SOC_MSR_SKX_H_ + +/* MCA_ERROR_CONTROL */ +#define U2C_SMI_ENABLED (1 << 2) + +/* IA32_ERR_CTRL */ +#define CORE_ERR_DISABLE (1 << 5) +#define CMCI_DISABLE (1 << 4) +#define UCE_TO_CE_DOWNGRADE (1 << 2) + +/* MSR_PKG_CST_CONFIG_CONTROL */ +#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) + +/* MSR_POWER_CTL (SKX and CPX) */ +#define FAST_BRK_SNP_ENABLE_SHIFT 3 +#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) +#define FAST_BRK_INT_ENABLE_SHIFT 4 +#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 +#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) +#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 +#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) +#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 +#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) +#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 +#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) +#define LTR_IIO_DISABLE_SHIFT 29 +#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) + +#endif /* _SOC_MSR_SKX_H_ */ |