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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-07-18 20:38:01 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:33:43 +0000 |
| commit | c1be66ee6003701106e27b7e43e8bbfc934f4c39 (patch) | |
| tree | 2f67cbf4acaa33c08f2aa41ee0cc505ac9f275ea /src/soc | |
| parent | e0850ad6a01fc4af730bac3d5fdb59e347af4cff (diff) | |
| download | coreboot-c1be66ee6003701106e27b7e43e8bbfc934f4c39.tar.gz coreboot-c1be66ee6003701106e27b7e43e8bbfc934f4c39.tar.bz2 coreboot-c1be66ee6003701106e27b7e43e8bbfc934f4c39.zip | |
soc/amd/glinda/root_complex: add non-PCI MMIO registers
Add the SoC-specific non-PCI MMIO register list. PPR #57254 Rev 1.52 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I29b4ef947776ab8a6c215c1a5204769a9f61e6fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/glinda/root_complex.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 4e6eaeda955c..86554ace7724 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -9,6 +9,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> #include <arch/ioapic.h> #include <arch/vga.h> #include <cbmem.h> @@ -236,3 +237,31 @@ struct device_operations glinda_root_complex_operations = { .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; + +uint32_t get_iohc_misc_smn_base(struct device *domain) +{ + return 0x13b10000; +} + +static const struct non_pci_mmio_reg non_pci_mmio[] = { + { 0x2d0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we + tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB + resource. */ + { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, + { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x310, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x320, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, +}; + +const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) +{ + *count = ARRAY_SIZE(non_pci_mmio); + return non_pci_mmio; +} |