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authorJon Murphy <jpmurphy@google.com>2022-06-28 10:36:23 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-07-04 14:02:26 +0000
commitc4e90454f4e3787c9e5d0b7aa758ee9b5757df4b (patch)
treead1a49b4477d62eb6604e3332b6ffc4a64daed06 /src/soc
parentdc86804a7db0ac67b81803d1662608320c8838a7 (diff)
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treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/Kconfig2
-rw-r--r--src/soc/amd/picasso/Kconfig2
-rw-r--r--src/soc/amd/sabrina/Kconfig2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h2
-rw-r--r--src/soc/rockchip/rk3399/spi_bitbang.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index bccd455a2a0c..d3a28413a8fa 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -434,7 +434,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 88ae228fb591..2a056a24529a 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -466,7 +466,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 2e9022f24ca9..654c6e393530 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -454,7 +454,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 322e9f3d02ad..f7aae1c0cdf0 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -490,7 +490,7 @@ uint8_t cse_wait_com_soft_temp_disable(void);
/*
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
- * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
+ * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is
* currently selected partition.
diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c
index 27b23f1ea36c..8bc45e50be70 100644
--- a/src/soc/rockchip/rk3399/spi_bitbang.c
+++ b/src/soc/rockchip/rk3399/spi_bitbang.c
@@ -46,7 +46,7 @@ static void set_cs(const struct spi_bitbang_ops *ops, int value)
gpio_set(slave->cs, value);
}
-/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */
+/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
static const struct rockchip_bitbang_slave slaves[] = {
[0] = {
.ops = { get_miso, set_mosi, set_clk, set_cs },