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| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 14:22:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-15 00:00:13 +0000 |
| commit | c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d (patch) | |
| tree | ca9cead4c93c5a0723234e27e93212890dc787d3 /src/soc | |
| parent | 7af90247be608ddb79b689e0bfded3caf1c11d07 (diff) | |
| download | coreboot-c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d.tar.gz coreboot-c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d.tar.bz2 coreboot-c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d.zip | |
soc/intel/broadwell/pcie.c: Simplify AND-mask
There's no need to mask out bit 11, as it is unconditionally set. For
some reason, this changes the resulting coreboot image. Also simplify
another PCI operation with a redundant AND-mask.
Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 28d858f2b092..29915d6e1352 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -516,8 +516,8 @@ static void pch_pcie_early(struct device *dev) } /* Enable LTR in Root Port. Disable OBFF. */ - pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11)); + pci_or_config32(dev, 0x68, 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); |