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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-01 13:55:10 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-01 23:37:11 +0200 |
| commit | ca7794854c9d04d1fcd95c2e1170265b8a36297b (patch) | |
| tree | 1b73d0a5e0539e6c3907bbb82ed635ad7bbdd3f3 /src/soc | |
| parent | 0232549621f37af5d13c370ba09a421755969194 (diff) | |
| download | coreboot-ca7794854c9d04d1fcd95c2e1170265b8a36297b.tar.gz coreboot-ca7794854c9d04d1fcd95c2e1170265b8a36297b.tar.bz2 coreboot-ca7794854c9d04d1fcd95c2e1170265b8a36297b.zip | |
tegra132: adjust vboot2 memlayout to make coreboot compile
romstage didn't fit in it's region anymore.
Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10759
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index a834f999144e..2fba8ef7e853 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,9 +36,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) - BOOTBLOCK(0x40019000, 24K) - VERSTAGE(0x4001f000, 60K) - ROMSTAGE(0x4002e000, 72K) + BOOTBLOCK(0x40019000, 22K) + VERSTAGE(0x4001e800, 58K) + ROMSTAGE(0x4002d000, 76K) SRAM_END(0x40040000) DRAM_START(0x80000000) |