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| author | Subrata Banik <subrata.banik@intel.com> | 2021-10-07 00:39:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-10-06 19:35:41 +0000 |
| commit | d6da4ef69e4ec8decbaee41297c3a96686021567 (patch) | |
| tree | db094f12a5fa741b155186dfa5e7813157b765e1 /src/soc | |
| parent | 78e66ad63b41316d268d33e1a68eeffe06b85baf (diff) | |
| download | coreboot-d6da4ef69e4ec8decbaee41297c3a96686021567.tar.gz coreboot-d6da4ef69e4ec8decbaee41297c3a96686021567.tar.bz2 coreboot-d6da4ef69e4ec8decbaee41297c3a96686021567.zip | |
soc/intel/alderlake: Skip setting D0I3 bit for HECI devices
This patch skips setting D0I3 bit for all HECI devices by FSP.
BUG=b:200644229
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.
Change-Id: I86d61c49b8f187611efd495712ad901184665f31
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ae25371cbd5..333957f2eaad 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -599,6 +599,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + /* Skip setting D0I3 bit for all HECI devices */ + s_cfg->DisableD0I3SettingForHeci = 1; /* * Power Optimizer for DMI * DmiPwrOptimizeDisable is default to 0. |