soc/amd/*/acpi: factor out common get_pstate_info implementation

The implementations of get_pstate_info of Picasso, Cezanne, Mendocino,
Phoenix and Glinda are identical, so factor it out and move it to the
common AMD SoC code. The SoC-specific get_pstate_core_freq and
get_pstate_core_power functions remain in the SoC-specific code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe0494f1747f381a75b3dd71a8cc38fdc6dce042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

7 files changed, 56 insertions, 222 deletions

diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 51c62cbe6b9c..057bd768505c 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -95,7 +95,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
-static uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(msr_t pstate_def)
 {
 	uint32_t core_freq, core_freq_mul, core_freq_div;
 	bool valid_freq_divisor;
@@ -133,7 +133,7 @@ static uint32_t get_pstate_core_freq(msr_t pstate_def)
 	return core_freq;
 }
 
-static uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(msr_t pstate_def)
 {
 	uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
 
@@ -181,48 +181,6 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 	return power_in_mw;
 }
 
-/*
- * Populate structure describing enabled p-states and return count of enabled p-states.
- */
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values)
-{
-	msr_t pstate_def;
-	size_t pstate_count, pstate;
-	uint32_t pstate_enable, max_pstate;
-
-	pstate_count = 0;
-	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
-
-	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_MSR(pstate));
-
-		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
-				>> PSTATE_DEF_HI_ENABLE_SHIFT;
-		if (!pstate_enable)
-			continue;
-
-		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
-		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
-		pstate_values[pstate_count].control_value = pstate;
-		pstate_values[pstate_count].status_value = pstate;
-
-		pstate_xpss_values[pstate_count].core_freq =
-			(uint64_t)pstate_values[pstate_count].core_freq;
-		pstate_xpss_values[pstate_count].power =
-			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
-		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
-		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
-		pstate_count++;
-	}
-
-	return pstate_count;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,
diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c
index cefa0e46a5f2..dbda621141eb 100644
--- a/src/soc/amd/common/block/acpi/cpu_power_state.c
+++ b/src/soc/amd/common/block/acpi/cpu_power_state.c
@@ -7,8 +7,51 @@
 #include <console/console.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/msr.h>
+#include <soc/msr.h>
 #include <types.h>
 
+/*
+ * Populate structure describing enabled p-states and return count of enabled p-states.
+ */
+static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+			      struct acpi_xpss_sw_pstate *pstate_xpss_values)
+{
+	msr_t pstate_def;
+	size_t pstate_count, pstate;
+	uint32_t pstate_enable, max_pstate;
+
+	pstate_count = 0;
+	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
+
+	for (pstate = 0; pstate <= max_pstate; pstate++) {
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
+
+		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
+				>> PSTATE_DEF_HI_ENABLE_SHIFT;
+		if (!pstate_enable)
+			continue;
+
+		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
+		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
+		pstate_values[pstate_count].transition_latency = 0;
+		pstate_values[pstate_count].bus_master_latency = 0;
+		pstate_values[pstate_count].control_value = pstate;
+		pstate_values[pstate_count].status_value = pstate;
+
+		pstate_xpss_values[pstate_count].core_freq =
+			(uint64_t)pstate_values[pstate_count].core_freq;
+		pstate_xpss_values[pstate_count].power =
+			(uint64_t)pstate_values[pstate_count].power;
+		pstate_xpss_values[pstate_count].transition_latency = 0;
+		pstate_xpss_values[pstate_count].bus_master_latency = 0;
+		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
+		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
+		pstate_count++;
+	}
+
+	return pstate_count;
+}
+
 static void write_cstate_entry(acpi_cstate_t *entry, const acpi_cstate_t *data,
 			       uint32_t cstate_io_base_address)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 998ed136fbea..76d032672517 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -4,6 +4,7 @@
 #define AMD_BLOCK_CPU_H
 
 #include <acpi/acpi.h>
+#include <cpu/x86/msr.h>
 #include <types.h>
 
 #define MAX_CSTATE_COUNT	8
@@ -14,8 +15,8 @@ unsigned int get_threads_per_core(void);
 void set_cstate_io_addr(void);
 void write_resume_eip(void);
 
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values);
+uint32_t get_pstate_core_freq(msr_t pstate_def);
+uint32_t get_pstate_core_power(msr_t pstate_def);
 const acpi_cstate_t *get_cstate_config_data(size_t *size);
 
 #endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 78e39cfe1f92..ff3f870fddb6 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -98,7 +98,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
-static uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(msr_t pstate_def)
 {
 	uint32_t core_freq, core_freq_mul, core_freq_div;
 	bool valid_freq_divisor;
@@ -136,7 +136,7 @@ static uint32_t get_pstate_core_freq(msr_t pstate_def)
 	return core_freq;
 }
 
-static uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(msr_t pstate_def)
 {
 	uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
 
@@ -184,48 +184,6 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 	return power_in_mw;
 }
 
-/*
- * Populate structure describing enabled p-states and return count of enabled p-states.
- */
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values)
-{
-	msr_t pstate_def;
-	size_t pstate_count, pstate;
-	uint32_t pstate_enable, max_pstate;
-
-	pstate_count = 0;
-	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
-
-	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_MSR(pstate));
-
-		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
-				>> PSTATE_DEF_HI_ENABLE_SHIFT;
-		if (!pstate_enable)
-			continue;
-
-		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
-		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
-		pstate_values[pstate_count].control_value = pstate;
-		pstate_values[pstate_count].status_value = pstate;
-
-		pstate_xpss_values[pstate_count].core_freq =
-			(uint64_t)pstate_values[pstate_count].core_freq;
-		pstate_xpss_values[pstate_count].power =
-			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
-		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
-		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
-		pstate_count++;
-	}
-
-	return pstate_count;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index a2990abe0a7c..01cdb94283ff 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -97,7 +97,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
-static uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(msr_t pstate_def)
 {
 	uint32_t core_freq, core_freq_mul, core_freq_div;
 	bool valid_freq_divisor;
@@ -135,7 +135,7 @@ static uint32_t get_pstate_core_freq(msr_t pstate_def)
 	return core_freq;
 }
 
-static uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(msr_t pstate_def)
 {
 	uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
 
@@ -183,48 +183,6 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 	return power_in_mw;
 }
 
-/*
- * Populate structure describing enabled p-states and return count of enabled p-states.
- */
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values)
-{
-	msr_t pstate_def;
-	size_t pstate_count, pstate;
-	uint32_t pstate_enable, max_pstate;
-
-	pstate_count = 0;
-	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
-
-	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_MSR(pstate));
-
-		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
-				>> PSTATE_DEF_HI_ENABLE_SHIFT;
-		if (!pstate_enable)
-			continue;
-
-		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
-		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
-		pstate_values[pstate_count].control_value = pstate;
-		pstate_values[pstate_count].status_value = pstate;
-
-		pstate_xpss_values[pstate_count].core_freq =
-			(uint64_t)pstate_values[pstate_count].core_freq;
-		pstate_xpss_values[pstate_count].power =
-			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
-		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
-		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
-		pstate_count++;
-	}
-
-	return pstate_count;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index ca60e8c721b4..2b7f592eaa23 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -98,7 +98,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
-static uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(msr_t pstate_def)
 {
 	uint32_t core_freq, core_freq_mul, core_freq_div;
 	bool valid_freq_divisor;
@@ -136,7 +136,7 @@ static uint32_t get_pstate_core_freq(msr_t pstate_def)
 	return core_freq;
 }
 
-static uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(msr_t pstate_def)
 {
 	uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
 
@@ -184,48 +184,6 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 	return power_in_mw;
 }
 
-/*
- * Populate structure describing enabled p-states and return count of enabled p-states.
- */
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values)
-{
-	msr_t pstate_def;
-	size_t pstate_count, pstate;
-	uint32_t pstate_enable, max_pstate;
-
-	pstate_count = 0;
-	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
-
-	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_MSR(pstate));
-
-		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
-				>> PSTATE_DEF_HI_ENABLE_SHIFT;
-		if (!pstate_enable)
-			continue;
-
-		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
-		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
-		pstate_values[pstate_count].control_value = pstate;
-		pstate_values[pstate_count].status_value = pstate;
-
-		pstate_xpss_values[pstate_count].core_freq =
-			(uint64_t)pstate_values[pstate_count].core_freq;
-		pstate_xpss_values[pstate_count].power =
-			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
-		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
-		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
-		pstate_count++;
-	}
-
-	return pstate_count;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index cce78cf942f8..25ea87ca52bc 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -99,7 +99,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
 }
 
-static uint32_t get_pstate_core_freq(msr_t pstate_def)
+uint32_t get_pstate_core_freq(msr_t pstate_def)
 {
 	uint32_t core_freq, core_freq_mul, core_freq_div;
 	bool valid_freq_divisor;
@@ -137,7 +137,7 @@ static uint32_t get_pstate_core_freq(msr_t pstate_def)
 	return core_freq;
 }
 
-static uint32_t get_pstate_core_power(msr_t pstate_def)
+uint32_t get_pstate_core_power(msr_t pstate_def)
 {
 	uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw;
 
@@ -185,48 +185,6 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 	return power_in_mw;
 }
 
-/*
- * Populate structure describing enabled p-states and return count of enabled p-states.
- */
-size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
-		       struct acpi_xpss_sw_pstate *pstate_xpss_values)
-{
-	msr_t pstate_def;
-	size_t pstate_count, pstate;
-	uint32_t pstate_enable, max_pstate;
-
-	pstate_count = 0;
-	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
-
-	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_MSR(pstate));
-
-		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
-				>> PSTATE_DEF_HI_ENABLE_SHIFT;
-		if (!pstate_enable)
-			continue;
-
-		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
-		pstate_values[pstate_count].power = get_pstate_core_power(pstate_def);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
-		pstate_values[pstate_count].control_value = pstate;
-		pstate_values[pstate_count].status_value = pstate;
-
-		pstate_xpss_values[pstate_count].core_freq =
-			(uint64_t)pstate_values[pstate_count].core_freq;
-		pstate_xpss_values[pstate_count].power =
-			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
-		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
-		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
-		pstate_count++;
-	}
-
-	return pstate_count;
-}
-
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,