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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 18:29:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-06 17:19:52 +0000 |
| commit | f773e12795b64d11920d8710d40f63e5791cf230 (patch) | |
| tree | df0963a616bb3455261c293fc45bc51d7b4e05e9 /src/soc | |
| parent | 949bce5adf377bf82734e98d74ff3896f08003cd (diff) | |
| download | coreboot-f773e12795b64d11920d8710d40f63e5791cf230.tar.gz coreboot-f773e12795b64d11920d8710d40f63e5791cf230.tar.bz2 coreboot-f773e12795b64d11920d8710d40f63e5791cf230.zip | |
soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
Picasso and newer don't implement the P_CNT register to control the CPU
duty cycle and also trap the C state control IO addresses directly in
the CPU, so those won't reach the FCH. This register is unused in the
Picasso code and not even defined any more in the Cezanne PPR. The
Picasso PPR does define this register, but since it's useless and might
even just be a leftover form a pre-Zen CPU generation, drop the define.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a3fb1a2d7da5..31f3ed689c1f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -47,7 +47,6 @@ #define TIMER_STS BIT(0) #define PM1_CNT_BLK 0x62 #define PM_TMR_BLK 0x64 -#define PM_CPU_CTRL 0x66 #define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 |