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| author | Subrata Banik <subratabanik@google.com> | 2022-10-31 17:35:50 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-11-16 08:44:32 +0000 |
| commit | f9c075d36d7f2d3070927bbe2df57ae08e904ea5 (patch) | |
| tree | 2199aade8434f070b1e110dc9d33305cb9737da7 /src/soc | |
| parent | 770e8e354665787e45616bfee1247ea939f99792 (diff) | |
| download | coreboot-f9c075d36d7f2d3070927bbe2df57ae08e904ea5.tar.gz coreboot-f9c075d36d7f2d3070927bbe2df57ae08e904ea5.tar.bz2 coreboot-f9c075d36d7f2d3070927bbe2df57ae08e904ea5.zip | |
soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB
This patch uses index 0x10 for IOE P2SB memory resource allocation
instead of static 0.
Additionally, switches to `mmio_resource` from `mmio_resource_kb`.
TEST=Able to build and boot Google/Rex and observed log as below.
Without the code change:
[SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
gran 0 limit 0 flags f0000200 index 0
With the code change:
[SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
gran 0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/p2sb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/p2sb.c b/src/soc/intel/meteorlake/p2sb.c index d700c707ea0b..ae9b9a403c53 100644 --- a/src/soc/intel/meteorlake/p2sb.c +++ b/src/soc/intel/meteorlake/p2sb.c @@ -35,7 +35,7 @@ void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) static void ioe_p2sb_read_resources(struct device *dev) { /* Add the fixed MMIO resource for IOM */ - mmio_resource_kb(dev, 0, IOM_BASE_ADDR / KiB, IOM_BASE_SIZE / KiB); + mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE); } static void p2sb_read_resources(struct device *dev) |