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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2021-01-25 10:46:16 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 08:20:19 +0000 |
| commit | fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9 (patch) | |
| tree | 529343d48b2e0938484a9ffd948cd0c938d50e0e /src/soc | |
| parent | aacbd66a8537fe4ec45109324caa89145e70c1bd (diff) | |
| download | coreboot-fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9.tar.gz coreboot-fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9.tar.bz2 coreboot-fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9.zip | |
soc/intel/*: Move prmrr_core_configure
Move prmrr_core_configure before clearing MCEs.
This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.
According to Document 565432 this should be no issue in regards to
SGX activation.
Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index a071337f9f1e..f2b14d73f647 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -48,6 +48,10 @@ static const struct reg_script core_msr_script[] = { void soc_core_init(struct device *cpu) { + /* Configure Core PRMRR for SGX. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + prmrr_core_configure(); + /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ @@ -66,10 +70,6 @@ void soc_core_init(struct device *cpu) */ enable_pm_timer_emulation(); - /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - prmrr_core_configure(); - /* Set Max Non-Turbo ratio if RAPL is disabled. */ if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1647db48555e..307c84955097 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -97,6 +97,10 @@ static void configure_c_states(void) /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* Configure Core PRMRR for SGX. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + prmrr_core_configure(); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -126,10 +130,6 @@ void soc_core_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); - - /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - prmrr_core_configure(); } static void per_cpu_smm_trigger(void) |