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authorJonathan Zhang <jonzhang@fb.com>2022-08-08 15:38:54 -0700
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-11-08 22:55:20 +0000
commitfe17a7d4d420763ef387e84256eaed0373c25725 (patch)
treeae5069dfc9631a2300b3437dfed03bee45310d35 /src/soc
parenta2503fa2e9c1c69495c29c4dfb00e7413952523d (diff)
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soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/Makefile.inc1
-rw-r--r--src/soc/intel/xeon_sp/cpx/Makefile.inc2
-rw-r--r--src/soc/intel/xeon_sp/cpx/romstage.c2
-rw-r--r--src/soc/intel/xeon_sp/cpx/upd_display.c8
-rw-r--r--src/soc/intel/xeon_sp/include/soc/fsp_upd.h (renamed from src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h)5
-rw-r--r--src/soc/intel/xeon_sp/skx/upd_display.c4
6 files changed, 12 insertions, 10 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index e5a5963aa486..bacbd6fffaee 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -19,5 +19,6 @@ postcar-y += spi.c
subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
+CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h
endif ## XEON_SP_COMMON_BASE
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc
index 0cd267b71259..d2a1583fe8ea 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc
@@ -16,8 +16,6 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp
-CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h
-
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b
endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index efdce78ca9e3..6ce5ef52acc7 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -154,7 +154,7 @@ static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
- FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
const struct device *dev;
const config_t *config = config_of_soc();
diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c
index ae5eeda09c07..33807d351f6b 100644
--- a/src/soc/intel/xeon_sp/cpx/upd_display.c
+++ b/src/soc/intel/xeon_sp/cpx/upd_display.c
@@ -12,8 +12,8 @@ void soc_display_fspm_upd_params(
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd)
{
- const FSPM_CONFIG *new;
- const FSPM_CONFIG *old;
+ const FSP_M_CONFIG *new;
+ const FSP_M_CONFIG *old;
old = &fspm_old_upd->FspmConfig;
new = &fspm_new_upd->FspmConfig;
@@ -31,8 +31,8 @@ void soc_display_fsps_upd_params(
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd)
{
- const FSPS_CONFIG *new;
- const FSPS_CONFIG *old;
+ const FSP_S_CONFIG *new;
+ const FSP_S_CONFIG *old;
old = &fsps_old_upd->FspsConfig;
new = &fsps_new_upd->FspsConfig;
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h
index 55b2e990dbdd..15ce96f9ff3f 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h
+++ b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h
@@ -3,7 +3,10 @@
#ifndef _FSP_UPD_H_
#define _FSP_UPD_H_
-/* Rename the FSP UPD structs to what they were historically called on other platforms. */
+/*
+ * Intel FSPs of XEON server platforms define FSPX_CONFIG
+ * instead of FSP_X_CONFIG, which is expected by coreboot.
+ */
#define FSP_T_CONFIG FSPT_CONFIG
#define FSP_M_CONFIG FSPM_CONFIG
#define FSP_S_CONFIG FSPS_CONFIG
diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c
index 84105dd6a426..c718a582f014 100644
--- a/src/soc/intel/xeon_sp/skx/upd_display.c
+++ b/src/soc/intel/xeon_sp/skx/upd_display.c
@@ -32,8 +32,8 @@ void soc_display_fsps_upd_params(
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd)
{
- const FSPS_CONFIG *new;
- const FSPS_CONFIG *old;
+ const FSP_S_CONFIG *new;
+ const FSP_S_CONFIG *old;
old = &fsps_old_upd->FspsConfig;
new = &fsps_new_upd->FspsConfig;