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| author | Felix Held <felix-coreboot@felixheld.de> | 2015-05-31 20:28:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-20 16:35:47 +0100 |
| commit | d2e8f6ad33c750853844c5674d1a1a926ad7d93a (patch) | |
| tree | fde712f291c184ad279f9c1f4634b49d07eac867 /src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | |
| parent | e536a4d91697fc49d865dfa5065d2cbb31cbc03f (diff) | |
| download | coreboot-d2e8f6ad33c750853844c5674d1a1a926ad7d93a.tar.gz coreboot-d2e8f6ad33c750853844c5674d1a1a926ad7d93a.tar.bz2 coreboot-d2e8f6ad33c750853844c5674d1a1a926ad7d93a.zip | |
southbridge/amd: add support for Bolton FCH
The Bolton FCH needs different firmware files than the Hudson FCH.
A small patch to vendorcode is probably needed to make the XHCI controller work.
XHCI_DEVID in pci_devs.h is probably wrong for Hudson.
Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index cfabaa23e40a..77d660cc4fba 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,7 +21,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -51,7 +51,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ @@ -71,6 +71,8 @@ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ +#endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ |