diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-06 23:53:09 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-13 10:03:38 +0200 |
| commit | e61dd0f7a2be83ce5ba87d74f7384111576ffd49 (patch) | |
| tree | a9f2c51500bbd8702cf039c8e620653d25c4b4d8 /src/southbridge/amd/cimx/sb900/late.c | |
| parent | 216a619a74d61f66e3d3e1d668028d11a8868b4d (diff) | |
| download | coreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.tar.gz coreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.tar.bz2 coreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.zip | |
southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900/late.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/late.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 3cd603ca7a84..7303bdceba6f 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -23,6 +23,8 @@ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ @@ -109,6 +111,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); } |