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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/amd/rs780 | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.gz coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.bz2 coreboot-b0f1988f893bf5f581917816b11e810309955143.zip | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/rs780')
| -rw-r--r-- | src/southbridge/amd/rs780/early_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.h | 8 |
4 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 7bc9435b5b60..ab75e5f57ffc 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -24,7 +24,7 @@ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBMISC_INDEX 0x60 -#define NBMC_INDEX 0xE8 +#define NBMC_INDEX 0xE8 static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index cfcddb29f302..30345bef1135 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -186,7 +186,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) printk(BIOS_DEBUG, "Dev ID %x\n", Value); if ((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB - u32 MMIOStart = 0xffffffff; + u32 MMIOStart = 0xffffffff; u32 MMIOLimit = 0; for (Reg = 0x10; Reg < 0x20; Reg+=4) { u32 BaseA, LimitA; @@ -449,7 +449,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulMinSidePortClock = 333*100; #endif - vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default + vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default // find the DDR memory frequency if (is_family10h()) { @@ -1109,8 +1109,8 @@ static void dual_port_configuration(struct device *nb_dev, struct device *dev) /* For single port GFX configuration Only * width: -* 000 = x16 -* 001 = x1 +* 000 = x16 +* 001 = x1 * 010 = x2 * 011 = x4 * 100 = x8 diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index ef40ffd0606a..f4f33efab78b 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -93,7 +93,7 @@ void static rs780_config_misc_clk(struct device *nb_dev) byte |= 1 << 0; pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); - /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ + /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ #endif diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index ce46d9676013..e96608eba9eb 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -22,10 +22,10 @@ #include "chip.h" #include "rev.h" -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 #define EXT_CONF_BASE_ADDRESS 0xE0000000 #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 |