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| author | Rudolf Marek <r.marek@assembler.cz> | 2010-12-13 19:59:13 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2010-12-13 19:59:13 +0000 |
| commit | c4369536da601a02b23cb936c16e54c0485ec21e (patch) | |
| tree | 6e62d3fac5226b775c021c34f2b6283d4f428ad9 /src/southbridge/amd/sb700/lpc.c | |
| parent | 59f410fa43e4176f2f4ded254ee4438f446b1c2d (diff) | |
| download | coreboot-c4369536da601a02b23cb936c16e54c0485ec21e.tar.gz coreboot-c4369536da601a02b23cb936c16e54c0485ec21e.tar.bz2 coreboot-c4369536da601a02b23cb936c16e54c0485ec21e.zip | |
Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well.
The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/sb700/lpc.c')
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a3a50c6c9b7c..c07323082129 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -28,6 +28,7 @@ #include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <cbmem.h> #include "sb700.h" static void lpc_init(device_t dev) @@ -63,6 +64,27 @@ static void lpc_init(device_t dev) byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + + /* hack, but the whole sb700 startup lacks any device which + is doing the acpi init */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + { + extern u8 acpi_slp_type; + u16 tmp = inw(ACPI_PM1_CNT_BLK); + acpi_slp_type = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); + } +#endif +} + +void set_cbmem_toc(struct cbmem_entry *toc) { + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } } static void sb700_lpc_read_resources(device_t dev) |