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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-23 22:28:26 -0500 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2015-10-25 05:05:46 +0100 |
| commit | ee3ec8e21256e544ef0a32f283a65c0c47040948 (patch) | |
| tree | e15929b289e4a4e9876f217223cf7e53415285e3 /src/southbridge/amd/sb700/lpc.c | |
| parent | 2a16acee6b5fe7c8007f29e6015e0eef443a9344 (diff) | |
| download | coreboot-ee3ec8e21256e544ef0a32f283a65c0c47040948.tar.gz coreboot-ee3ec8e21256e544ef0a32f283a65c0c47040948.tar.bz2 coreboot-ee3ec8e21256e544ef0a32f283a65c0c47040948.zip | |
southbridge/amd/sb700: Set up uninitialized devices in early boot
LPC decodes were not enabled, leading to a failure of POST 80 cards
and similar debugging devices. Enable the relevant LPC decodes
to allow debugging.
Additionally, the SMBUS controllers were not properly set up.
Enable both the primary and auxiliary controllers.
Finally, K10 and higher CPUs were hanging during boot due to
a misconfigued IOAPIC. Properly configure the IOAPIC.
Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12177
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/sb700/lpc.c')
| -rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a39ec1849eca..0cc1e8bd3cac 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,6 +46,8 @@ static void lpc_init(device_t dev) u32 dword; device_t sm_dev; + printk(BIOS_SPEW, "%s\n", __func__); + /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); |