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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-23 15:56:30 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-03 13:44:54 +0000 |
| commit | 00ad8dfa181e627cbf566c575d1b95ffc7e435af (patch) | |
| tree | 3db499a0763fd1439d19b05eb9faa49e24081f40 /src/southbridge/amd/sr5650 | |
| parent | 92b5296a7ba1d6368ea425d71bcbf804b0ec97c7 (diff) | |
| download | coreboot-00ad8dfa181e627cbf566c575d1b95ffc7e435af.tar.gz coreboot-00ad8dfa181e627cbf566c575d1b95ffc7e435af.tar.bz2 coreboot-00ad8dfa181e627cbf566c575d1b95ffc7e435af.zip | |
device/pci_ops: Drop unused parameter
Drop the bus parameter, we do not use it.
It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.
Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/amd/sr5650')
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9d4c68975928..763dd014af19 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -888,7 +888,6 @@ void config_gpp_core(struct device *nb_dev, struct device *sb_dev) void pcie_config_misc_clk(struct device *nb_dev) { u32 reg; - //struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; @@ -902,9 +901,9 @@ void pcie_config_misc_clk(struct device *nb_dev) set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~(1 << 16); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); } if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { @@ -914,9 +913,9 @@ void pcie_config_misc_clk(struct device *nb_dev) set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~(1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); } #endif |