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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-15 18:21:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-20 14:40:46 +0000 |
| commit | 9bcbdbf9e48f3977cf5d48732527bbf02fea02de (patch) | |
| tree | 3816727d783eb72f753acfe045bf1f6080752497 /src/southbridge/amd | |
| parent | 2dfce0fd94cdad6b7b60c8c54dd8ed8438eb613e (diff) | |
| download | coreboot-9bcbdbf9e48f3977cf5d48732527bbf02fea02de.tar.gz coreboot-9bcbdbf9e48f3977cf5d48732527bbf02fea02de.tar.bz2 coreboot-9bcbdbf9e48f3977cf5d48732527bbf02fea02de.zip | |
nb,sb/amd/pi/*/pci_devs: drop unused PCI device IDs
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/pci_devs.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index ec92d977f3b7..ff06b0204c64 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -8,12 +8,10 @@ /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define XHCI2_DEV 0x10 #define XHCI2_FUNC 1 -#define XHCI2_DEVID 0x7814 #define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) /* SATA */ @@ -33,7 +31,6 @@ #define OHCI3_FUNC 0 #define OHCI4_DEV 0x14 #define OHCI4_FUNC 5 -#define OHCI_DEVID 0x7807 #define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) #define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) #define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) @@ -46,7 +43,6 @@ #define EHCI2_FUNC 2 #define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 -#define EHCI_DEVID 0x7808 #define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) #define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) #define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) @@ -54,32 +50,27 @@ /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 -#define HDA_DEVID 0x780D #define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_DEV PCU_DEV #define LPC_FUNC 3 -#define LPC_DEVID 0x780E #define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ #define SB_PCI_PORT_DEV 0x14 #define SB_PCI_PORT_FUNC 4 -#define SB_PCI_PORT_DEVID 0x780F #define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 -#define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #endif /* _PI_HUDSON_PCI_DEVS_H_ */ |