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| author | Furquan Shaikh <furquan@google.com> | 2014-04-22 10:41:05 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-04-26 13:27:09 +0200 |
| commit | 20f25dd5c8a513ee136e9f6d8c67959591298617 (patch) | |
| tree | e42f5cfe77fb4f73d3b8eb759f5faa328997efc8 /src/southbridge/broadcom | |
| parent | 817149643c27fca022cf526d6113a4aff898d511 (diff) | |
| download | coreboot-20f25dd5c8a513ee136e9f6d8c67959591298617.tar.gz coreboot-20f25dd5c8a513ee136e9f6d8c67959591298617.tar.bz2 coreboot-20f25dd5c8a513ee136e9f6d8c67959591298617.zip | |
Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.
Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/broadcom')
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/early_setup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 60f7abbc5f8c..9dee295c0d09 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -177,7 +177,7 @@ static void bcm5785_early_setup(void) byte |= (1<<0); // SATA enable pci_write_config8(dev, 0x84, byte); -// WDT and cf9 for later in coreboot_ram to call hard_reset +// WDT and cf9 for later in ramstage to call hard_reset bcm5785_enable_wdt_port_cf9(); bcm5785_enable_msg(); |