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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 14:47:47 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-16 08:58:50 +0000 |
| commit | e2f0a5f76c8a525396f627b8ba97e8913ab14fc6 (patch) | |
| tree | 201919537965cd897ad3e50afe07b1ea4153a050 /src/southbridge/intel/bd82x6x/Makefile.inc | |
| parent | ad0b48222ffd894f1b8f78e7de8a6ee139fc17c9 (diff) | |
| download | coreboot-e2f0a5f76c8a525396f627b8ba97e8913ab14fc6.tar.gz coreboot-e2f0a5f76c8a525396f627b8ba97e8913ab14fc6.tar.bz2 coreboot-e2f0a5f76c8a525396f627b8ba97e8913ab14fc6.zip | |
sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.
Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 24d7e2d24e9b..7ce3da70adfe 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,7 +38,7 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c early_pch_common.c +romstage-y += early_spi.c romstage-y += early_rcba.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -47,6 +47,4 @@ else romstage-y += early_me_mrc.c early_usb_mrc.c endif -ramstage-y += early_pch_common.c - endif |