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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 17:06:47 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-25 22:25:22 +0200 |
| commit | 800e950d646d687aa4231e8eced06a0615ba7344 (patch) | |
| tree | 18213cc8691ec4c45211842dedfcea2da7e0d843 /src/southbridge/intel/bd82x6x/lpc.c | |
| parent | 27e5aacc522a4ce97ffd8d57a93042d9703d70fe (diff) | |
| download | coreboot-800e950d646d687aa4231e8eced06a0615ba7344.tar.gz coreboot-800e950d646d687aa4231e8eced06a0615ba7344.tar.bz2 coreboot-800e950d646d687aa4231e8eced06a0615ba7344.zip | |
ELOG: Log boot-time events found in southbridge
This is called from the SMI handler install because those
setup functions clear many of these registers.
Ensure that these events show up in the log as appropriate.
Example log output:
159 | 2012-06-23 14:31:54 | SUS Power Fail
160 | 2012-06-23 14:31:54 | System Reset
161 | 2012-06-23 14:31:54 | ACPI Wake | S5
Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5f81edf394a1..ae719992386e 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -29,6 +29,7 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> +#include <elog.h> #include "pch.h" #define NMI_OFF 0 @@ -296,6 +297,9 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); +#if CONFIG_ELOG + elog_add_event(ELOG_TYPE_RTC_RESET); +#endif } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |