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authorAngel Pons <th3fanbus@gmail.com>2021-01-27 12:25:52 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-02-13 10:59:49 +0000
commit5deff30059d7266336bc3a543b4212533add7e2e (patch)
treeb53464cc8d6f66299472e80bdd5cd5549ce2a761 /src/southbridge/intel/bd82x6x/me.c
parentc94bc8e2d092c6f3784007e046a1295c05ad78e2 (diff)
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sb/intel/bd82x6x: Move ME SMM code into a separate file
This allows dropping some preprocessor usage. The `mkhi_end_of_post` static functions had to be renamed to avoid a name clash. A follow-up will tidy up the code in me_smm.c to reduce some duplication. Change-Id: I6357fed3540be87f42d1fd59534666b9092d0652 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49991 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.c')
-rw-r--r--src/southbridge/intel/bd82x6x/me.c77
1 files changed, 0 insertions, 77 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index e81d7ff7b353..cb263622cc9f 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -27,81 +27,6 @@
#include "me.h"
#include "pch.h"
-#ifdef __SIMPLE_DEVICE__
-
-/* Send END OF POST message to the ME */
-static int mkhi_end_of_post(void)
-{
- struct mkhi_header mkhi = {
- .group_id = MKHI_GROUP_ID_GEN,
- .command = MKHI_END_OF_POST,
- };
- struct mei_header mei = {
- .is_complete = 1,
- .host_address = MEI_HOST_ADDRESS,
- .client_address = MEI_ADDRESS_MKHI,
- .length = sizeof(mkhi),
- };
-
- /* Send request and wait for response */
- if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) {
- printk(BIOS_ERR, "ME: END OF POST message failed\n");
- return -1;
- }
-
- printk(BIOS_INFO, "ME: END OF POST message successful\n");
- return 0;
-}
-
-static void intel_me7_finalize_smm(void)
-{
- struct me_hfs hfs;
- u32 reg32;
-
- update_mei_base_address();
-
- /* S3 path will have hidden this device already */
- if (!is_mei_base_address_valid())
- return;
-
- /* Make sure ME is in a mode that expects EOP */
- reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
- memcpy(&hfs, &reg32, sizeof(u32));
-
- /* Abort and leave device alone if not normal mode */
- if (hfs.fpt_bad ||
- hfs.working_state != ME_HFS_CWS_NORMAL ||
- hfs.operation_mode != ME_HFS_MODE_NORMAL)
- return;
-
- /* Try to send EOP command so ME stops accepting other commands */
- mkhi_end_of_post();
-
- /* Make sure IO is disabled */
- pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
- ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
-
- /* Hide the PCI device */
- RCBA32_OR(FD2, PCH_DISABLE_MEI1);
-}
-
-void intel_me_finalize_smm(void)
-{
- u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID);
- switch (did) {
- case 0x1c3a:
- intel_me7_finalize_smm();
- break;
- case 0x1e3a:
- intel_me8_finalize_smm();
- break;
- default:
- printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did);
- }
-}
-
-#else
-
/* Determine the path that we should take based on ME status */
static me_bios_path intel_me_path(struct device *dev)
{
@@ -366,5 +291,3 @@ static const struct pci_driver intel_me __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x1c3a,
};
-
-#endif /* __SIMPLE_DEVICE__ */