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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-31 16:50:05 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-01-15 09:34:33 +0000 |
| commit | a48debdaa0124c57bef67c9ac90e955e69671d56 (patch) | |
| tree | f173f31da6fd609978a043acd7dbb698bd0550fa /src/southbridge/intel/bd82x6x | |
| parent | d323d844f743e2876e404cf13ddd32a1bd050715 (diff) | |
| download | coreboot-a48debdaa0124c57bef67c9ac90e955e69671d56.tar.gz coreboot-a48debdaa0124c57bef67c9ac90e955e69671d56.tar.bz2 coreboot-a48debdaa0124c57bef67c9ac90e955e69671d56.zip | |
sb/intel/bd82x6x/early_usb: Add USB TX/RX gains
Describe the USB 'current' settings based on MRC.bin that converts
the USB trace length to a predefined register value.
MRC.bin decides which setting to use based on the PC type, mobile
or desktop, and the trace length.
Tested: Lenovo X220 still boots.
Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 13 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 12 |
2 files changed, 19 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 974c19038128..35bfeca37dd3 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -16,26 +16,27 @@ void early_usb_init(const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, - 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, - 0x20000353 }; + const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, + USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, + USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 }; int i; /* Unlock registers. */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) { - if (portmap[i].enabled && !pch_is_mobile() && portmap[i].current == 0) { + if (portmap[i].enabled && !pch_is_mobile() && + currents[portmap[i].current] == USBIR_TXRX_GAIN_MOBILE_LOW) { /* * Note for developers: You can fix this by re-running autoport on * vendor firmware and then updating portmap currents accordingly. * If that is not possible, another option is to choose a non-zero * current setting. In either case, please test all the USB ports. */ - printk(BIOS_ERR, "%s: USB%02d: current setting of 0 is an invalid setting for desktop!\n", + printk(BIOS_ERR, "%s: USB%02d: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!\n", __func__, i); - RCBA32(USBIR0 + 4 * i) = currents[1]; + RCBA32(USBIR0 + 4 * i) = USBIR_TXRX_GAIN_DEFAULT; } else { RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 88c8df5c4a25..040b477d3592 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -382,6 +382,18 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define USBIR12 0x3530 /* 32bit */ #define USBIR13 0x3534 /* 32bit */ +/* Up to 5" onboard trace length */ +#define USBIR_TXRX_GAIN_MOBILE_LOW 0x20000153 + +/* Up to 6" onboard trace length */ +#define USBIR_TXRX_GAIN_DESKTOP_LOW 0x20000F53 + +/* Up to 14" onboard trace length, up to 8" on wires */ +#define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 + +/* Up to 10" onboard trace length, up to 15" on wires */ +#define USBIR_TXRX_GAIN_HIGH 0x2000055B + /* Miscellaneous Control Register */ #define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ |