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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 14:41:45 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-13 14:48:25 +0000 |
| commit | 1ae592b468d7b40d8c7f50d4fcb4dd515aeeaf74 (patch) | |
| tree | e9beab37497118594492cf8cc5669b0f9efbb782 /src/southbridge/intel/common/Makefile.inc | |
| parent | 6d569163ab680ca436b16c040e6840e969df6c61 (diff) | |
| download | coreboot-1ae592b468d7b40d8c7f50d4fcb4dd515aeeaf74.tar.gz coreboot-1ae592b468d7b40d8c7f50d4fcb4dd515aeeaf74.tar.bz2 coreboot-1ae592b468d7b40d8c7f50d4fcb4dd515aeeaf74.zip | |
sb/intel/common: Add common detect_s3_resume
Add a common detect_s3_resume function.
Will be used by other southbridge code.
TODO: Merge with soc/intel/common/*/pmclib
Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I283a841575430f2f179997db8d2f08fa3978a0bb applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.
Change-Id: I88023af522afac8164f068b0fbe0eac601aef702
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3ad79248a07f..ac339a29159f 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,6 +25,8 @@ postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c |