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| author | John Su <john_su@compal.corp-partner.google.com> | 2025-04-28 11:03:43 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2025-04-28 15:59:45 +0000 |
| commit | 92955fbfa6571a6c1d35d8c14cd9f05c182ff82f (patch) | |
| tree | 5462deb993a1cf910243fc58cd04e1481cd3921e /src/southbridge/intel/common/me.h | |
| parent | aafcb01ec42ca099a9b82f88c32638b3bb625f7e (diff) | |
| download | coreboot-main.tar.gz coreboot-main.tar.bz2 coreboot-main.zip | |
GPP_E9 was wrongly configured to NF1 instead of NF2 i.e. ISH_GP4.
Reference: Intel doc#648094
BUG=b:410645679
TEST=Check GPIO config in the OS.
Change-Id: I43e3ec2e29138d59ed82e5ff4b264ab8dc3a39fb
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87471
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/southbridge/intel/common/me.h')
0 files changed, 0 insertions, 0 deletions