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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2019-02-15 11:55:20 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-02-28 09:26:01 +0000 |
| commit | db9e9ac30d12ac4fa548c01b907193503a5ae421 (patch) | |
| tree | 6c35b66ab58a5b9d0c40f436e7cdc1b1cd8d3872 /src/southbridge/intel/fsp_rangeley/spi.c | |
| parent | ba8af5807c83244c947571caa7f3c488f4e581a1 (diff) | |
| download | coreboot-db9e9ac30d12ac4fa548c01b907193503a5ae421.tar.gz coreboot-db9e9ac30d12ac4fa548c01b907193503a5ae421.tar.bz2 coreboot-db9e9ac30d12ac4fa548c01b907193503a5ae421.zip | |
soc/intel/cannonlake: Add PCH series check for CML LP PCH
TEST=Verify PM_STS1 value is is not 0xFF.
Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/spi.c')
0 files changed, 0 insertions, 0 deletions