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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-22 20:26:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-03 13:29:08 +0000 |
| commit | 19cb6c9980f86bb602c988f48dbf20413f2c27bf (patch) | |
| tree | ed6d49fb1b3e38d935d8e257988ac483364cfb59 /src/southbridge/intel/fsp_rangeley | |
| parent | 9c8895fd889b01fe71bb296e2566b96a9542b303 (diff) | |
| download | coreboot-19cb6c9980f86bb602c988f48dbf20413f2c27bf.tar.gz coreboot-19cb6c9980f86bb602c988f48dbf20413f2c27bf.tar.bz2 coreboot-19cb6c9980f86bb602c988f48dbf20413f2c27bf.zip | |
sb/intel/fsp_rangeley: Remove variable set but not used
Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 19e470e30981..2c2427eed1c9 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -90,7 +90,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; timestamp_add_now(TS_AFTER_INITRAM); @@ -113,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); |