diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-04 15:39:44 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-01-10 13:25:57 +0100 |
| commit | 3d0288d6767fc4b0ddeb270392a22bf1894767cd (patch) | |
| tree | ca55c60171419fc9623f5d297f5896e2ba6078b4 /src/southbridge/intel/i82801dx | |
| parent | f2f4b78dd2c5a0b79e1ef239d605f92e1caeb55a (diff) | |
| download | coreboot-3d0288d6767fc4b0ddeb270392a22bf1894767cd.tar.gz coreboot-3d0288d6767fc4b0ddeb270392a22bf1894767cd.tar.bz2 coreboot-3d0288d6767fc4b0ddeb270392a22bf1894767cd.zip | |
intel/i82801dx: Support 2MiB FWH part
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.
Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17918
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/bootblock.c | 21 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index af8300e8edf2..82db1c3752df 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -29,4 +29,8 @@ config EHCI_BAR hex default 0xfef00000 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801dx/bootblock.c" + endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c new file mode 100644 index 000000000000..8ae419dd9bf6 --- /dev/null +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +static void bootblock_southbridge_init(void) +{ + /* Set FWH IDs for 2 MB flash part. */ + if (CONFIG_ROM_SIZE == 0x200000) + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111); +} |