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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:32:56 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-23 05:22:57 +0000 |
| commit | 66faf0c286e30e22eb4eb120b95f34e2723ebd32 (patch) | |
| tree | a985dd62e009cc4bb304e9b153d63f3c97e1f8e6 /src/southbridge/intel/i82801dx | |
| parent | 17c59f5da533eddef5e6bb85866b6d933e7fb767 (diff) | |
| download | coreboot-66faf0c286e30e22eb4eb120b95f34e2723ebd32.tar.gz coreboot-66faf0c286e30e22eb4eb120b95f34e2723ebd32.tar.bz2 coreboot-66faf0c286e30e22eb4eb120b95f34e2723ebd32.zip | |
sb/intel/i82801dx: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I36f064b67f14556e38b41b7f64c3e27d8d935367
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 10 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index a4eb0481c5a9..cc70fdd9e8c5 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -20,7 +20,7 @@ #include <device/pci_ids.h> #include "i82801dx.h" -void i82801dx_enable(device_t dev) +void i82801dx_enable(struct device *dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -28,7 +28,7 @@ void i82801dx_enable(device_t dev) // all 82801dbm devices are in bus 0 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc - device_t lpc_dev = dev_find_slot(0, devfn); // 0 + struct device *lpc_dev = dev_find_slot(0, devfn); // 0 if (!lpc_dev) return; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 14ca28f9aa32..8c7da55ff14e 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -32,7 +32,7 @@ #if !defined(__ASSEMBLER__) #if !defined(__SIMPLE_DEVICE__) #include "chip.h" -extern void i82801dx_enable(device_t dev); +extern void i82801dx_enable(struct device *dev); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 0f0bbcfeacc9..925251da2ab7 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -81,7 +81,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -96,7 +96,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); } -static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -175,7 +175,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -217,7 +217,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -301,7 +301,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res; |