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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-16 01:04:24 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 14:54:39 +0000 |
| commit | cf2783882f914c2a50d06a7a31130ecb0b160f05 (patch) | |
| tree | 9a966d9efc9a347c376008e035a9884d7e21bca5 /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | e6e5ecb7e813fa151c558c739d5394dce0a2af8e (diff) | |
| download | coreboot-cf2783882f914c2a50d06a7a31130ecb0b160f05.tar.gz coreboot-cf2783882f914c2a50d06a7a31130ecb0b160f05.tar.bz2 coreboot-cf2783882f914c2a50d06a7a31130ecb0b160f05.zip | |
mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage
With the i82801gx code automatically disabling devices ethernet
NICs attached to the southbridge PCIe ports can now be disabled
during the ramstage.
Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30245
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index e664eb43fad6..66d47ae1577b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -272,12 +272,6 @@ int southbridge_detect_s3_resume(void); * Not all features might be disabled on * all chipsets. Esp. ICH-7U is picky. */ -#define FD_PCIE6 (1 << 21) -#define FD_PCIE5 (1 << 20) -#define FD_PCIE4 (1 << 19) -#define FD_PCIE3 (1 << 18) -#define FD_PCIE2 (1 << 17) -#define FD_PCIE1 (1 << 16) #define ICH_DISABLE_PCIE(x) (1 << (16 + (x))) #define FD_EHCI (1 << 15) #define FD_LPCB (1 << 14) |