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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:24:55 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:34:10 +0200 |
| commit | e99194555b9cb07bacc3008ec78ec61a949b47b9 (patch) | |
| tree | 7a3b5846fc491de0877b5c07405dac735e60586c /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | 671909b891439683d81420fe107025ded4caf88d (diff) | |
| download | coreboot-e99194555b9cb07bacc3008ec78ec61a949b47b9.tar.gz coreboot-e99194555b9cb07bacc3008ec78ec61a949b47b9.tar.bz2 coreboot-e99194555b9cb07bacc3008ec78ec61a949b47b9.zip | |
southbridge/intel/i82801gx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I08fb52ca13a4355d95fe31516c43de18d40de140
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 17b70267338d..d4adc182cad6 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -15,6 +15,9 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H + +#include <arch/acpi.h> + /* * It does not matter where we put the SMBus I/O base, as long as we * keep it consistent and don't interfere with other devices. Stage2 @@ -319,8 +322,6 @@ int southbridge_detect_s3_resume(void); #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) |