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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-02 23:29:07 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-05 13:21:55 +0000 |
| commit | f9891c8b469232cca28f0b12f613274f127748df (patch) | |
| tree | b10131ca552bcce69e92490a5f4a76575405387a /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | ad787e18e0ed24495132d0e9e638ed835afad354 (diff) | |
| download | coreboot-f9891c8b469232cca28f0b12f613274f127748df.tar.gz coreboot-f9891c8b469232cca28f0b12f613274f127748df.tar.bz2 coreboot-f9891c8b469232cca28f0b12f613274f127748df.zip | |
kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset
The extra PCI bus RST# and 200ms delay there was workaround
for custom add-on hardware.
Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index fec891982f2b..d615b403ac1d 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,8 +39,6 @@ void i82801gx_enable(struct device *dev); #endif -void ich7_p2p_secondary_reset(void); - void enable_smbus(void); #if ENV_ROMSTAGE |